1. Technical Field
The present invention relates generally to integrated circuit design, and more particularly, relates to a system, method and program product for designing an IC for signal integrity due to well proximity effects.
2. Related Art
In very large scale integrated (VLSI) circuit design, the proximity of a transistor's source or drain diffusion to a well edge affects its threshold voltage. Transistors designed in the same technology, even on the same integrated circuit (IC), will have different threshold voltages (Vt) depending on their active area's proximity to an implanted well edge. For example, FIG. 1 illustrates conventional complementary metal oxide semiconductor (CMOS) p-type field effect transistors (FET) 10 including a first device 12, a second device 14 and a third device 16. Devices 12, 14, 16 are located over an n-type well 20 that is positioned within a p-type substrate 22. An area 24 is considered an active area. Each device 12, 14, 16 is formed by the intersection of the gate polysilicon and active area 24. A distance D1 between a device edge 30 of first device 12 and an edge 32 of n-well 20 is sufficiently large enough to ensure that the threshold voltage Vt of first device 12 is as predicted by a device model. However, distance D2 between a device edge 34 of third device 16 and an edge 36 of n-well 20 is close enough so that third device 16 will have a threshold voltage Vt shift relative to a predicted device model.
Devices with a lower threshold voltage (Vt) have a greater sensitivity to electrical noise compared to more robust transistors. Depending on the expected sources of electrical noise and the required robustness of the IC design, it may or may not be desirable to place all transistors far enough away from a well edge to eliminate the effect. For example, in dense designs where circuits are robust and insensitive to noise, the well edge can be as close as allowed by the technology's design rules. In contrast, in noise sensitive designs, circuits that functionally fail due to noise can be modified if the devices are moved away from the well edge.
The conventional approach to testing signal integrity or signal noise analysis is to use computer-based tools to address those issues only. When one of these tools indicates a signal integrity failure, a designer must review the output from the tool and manually change his/her design to attempt to correct the failure, e.g., guess at which device caused the failure and move an edge of that device away from a well edge. Subsequently, the designer must re-execute the signal integrity analysis to determine whether the change corrected the failure. If the change did not fix the failure, the process is repeated. Therefore, this approach is time consuming and resource intensive. In view of the foregoing, there is a need in the art for an IC design method, system and program product that does not suffer from the problems of the related art.